同步清零
library ieee;
use ieee.std_logic_1164.all;
entity dchu is
port (clk,d:in std_logic;
q:out std_logic;
sclk:in std_logic);
end;
architecture ffq of dchu is signal q1:std_logic;
begin
process (sclk,clk,q1)
begin
if clk'event and clk='1' then
if sclk='1' then
q1<='0';
else q1<=d;
end if;
end if;
end process;
q<=q1; end ffq;
異步置位
apre library ieee;
use ieee.std_logic_1164.all;
entity dchu is port ( clk : in std_logic;
d : in std_logic;
q :out std_logic;
apre :in std_logic
); e
nd;
architecture ffq of dchu is signal
q1:std_logic;
begin process (apre,clk,q1)
begin if apre='1'
then q1<='1';
elsif clk'event and clk='1'
then q1<=d;
end if;
end process;
q<=q1; end ffq;